One approach to achieving sub-10 nm geometry devices would co-integrate Si/Ge with a Group III-V compound semiconductor material. The Group III-V material could be a binary material such, as for example, Gallium Arsenide (GaAs) or Gallium Antimonide (GaSb). The Group III-V material could also be a tertiary material such as, for example, Indium Gallium Arsenide (InGaAs) or Indium Gallium Antimonide (InGaSb).
Wafer bonding could be used to achieve the co-integration of the Si/Ge with the Group III-V material. However, bonding two such dissimilar materials on Silicon is difficult to perform in a reliable and repeatable manner.